Current Issue : April - June Volume : 2020 Issue Number : 2 Articles : 5 Articles
An improved operational transconductance amplifier (OTA) is presented in this work.\nThe fully differential OTA adopts the current recycling technique and complementary NMOS and\nPMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher\ncurrent efficiency, a data-driven biasing circuit was developed to dynamically adjust the power\nconsumption of the amplifier. Two comparators were added to detect the voltage difference at the\ninput nodes, and when the differential input is large enough to activate either comparator, extra\nbiasing current is activated and poured into the amplifier to enhance its slew rate and gain-bandwidth\nproduct (GBW). The threshold voltage of the complementary recycling folded cascode (CRFC)-based\ncomparator is configured to suppress overshoot. Complementary common-mode feedback (CMFB)\ntopology with local CMFB structure is built to acquire high common-mode gain. The OTA was\nfabricated in SMIC 0.18-microm CMOS technology. The experimental result based on a capacitive\nfeedback loop shows that the data-driven operation improves the average slew rate of the amplifier\nfrom 10.2 V/micros to 55.5 V/micros while the power only increases by 150%. The OTA has good potential to\nsatisfy the fast settling demands for capacitive sensing circuits....
To get a better tradeoff between the transient performance and current efficiency of Digital\nLow-Dropout(DLDO) regulator, this paper proposes an all-digital Low-Dropout(LDO) regulator\nwith adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC)\nwhose output frequency can be changed seamlessly. The frequency of sample clock and loop gain\nboost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO\nintegrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power.\nThe proposed DLDO is simulated at Semiconductor Manufacturing International Corporation\n(SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage\nof proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured\nvoltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA....
This work proposes a new simplified five-parameter estimation method for a single-diode\nmodel of photovoltaic panels. The method, based on an iterative algorithm, is able to estimate the\nparameter of the electrical single-diode model from the panelâ??s datasheet. Two iterative steps are\nused to estimate the five parameters starting from data provided by the manufacturer (nameplate\nvalues or Iâ??V curves). The first step permits finding the optimal value of the diode ideality factor A,\nand the second step allows the calculation of the Rp value to improve the accuracy. A model that\ntakes into account variations in temperature and solar irradiance has been used to validate the\nbehavior of the output parameters. Compared to other estimation work, the proposed method\nshows the best result in the standard test condition (STC) and with a variable solar irradiance.\nIndeed, the optimization of the A, Rs, and Rp parameters allows guaranteeing the minimum error\nbetween Iâ??V curves obtained from method and datasheet....
In this study, the effects of back-gate bias on the subthreshold swing (S) of a tunnel\nfield-effect transistor (TFET) were discussed. The electrostatic characteristics of the back-gated TFET\nwere obtained using technology computer-aided design (TCAD) simulation and were explained\nusing the concepts of turn-on and inversion voltages. As a result, S decreased, when the back-gate\nvoltage increased; this behavior is attributed to the resultant increase in inversion voltage. In addition,\nit was found that the onâ??off current ratio of the TFET increased with a decrease in S due to the\nback-gate voltage....
This paper presents the design and experimental characterization of a portable highprecision\nsingle-phase lock-in instrument with phase adjustment. The core consists of an analog\nlock-in amplifier IC prototype, integrated in 0.18 microm CMOS technology with 1.8 V supply, which\nfeatures programmable gain and operating frequency, resulting in a versatile on-chip solution with\npower consumption below 834 microW. It incorporates automatic phase alignment of the input and\nreference signals, performed through both a fixed -90Degreeand a 4-bit digitally programmable phase\nshifter, specifically designed using commercially available components to operate at 1 kHz\nfrequency. The system is driven by an Arduino YUN board, thus overall conforming a low-cost\nautonomous signal recovery instrument to determine, in real time, the electrical equivalent of\nresistive and capacitive sensors with a sensitivity................................
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